Japanese Patent Application Publication No. 2008-135522 (hereinafter referred to as Patent Literature 1) discloses an insulated gate semiconductor device that has an element region having a MOS structure provided therein, and an outer circumferential region around the element region. The element region has a plurality of gate trenches provided therein, and a gate insulating film and a gate electrode are provided in each of the gate trenches. In a range exposed on a bottom surface of the gate trench, a p-type bottom surface surrounding region (hereinafter referred to as an element portion bottom surface surrounding region) is provided. In the outer circumferential region, a plurality of trenches are provided to surround the element region, and each of the trenches is filled with an insulating layer. In a range exposed on a bottom surface of each of the trenches in the outer circumferential region, a p-type bottom surface surrounding region (hereinafter referred to as an outer circumferential portion bottom surface surrounding region) is provided. When a MOSFET is turned off, a depletion layer spreads in the element region, from the element portion bottom surface surrounding region into a drift region. This promotes depletion of the drift region in the element region. Moreover, a depletion layer spreads in the outer circumferential region, from the outer circumferential portion bottom surface surrounding region into the drift region. This promotes depletion of the drift region in the outer circumferential region. Accordingly, the withstand voltage of the insulated gate semiconductor device is improved.